• 開発元:半導体メーカー、産業用カメラメーカー、研究機関
  • 用途:放送用ENGカメラ、スポーツ放送向け高速高精細カメラなど



A 33Mpixel CMOS imager with multi-functional 3-stage pipeline ADC for 480fps high-speed mode and 120fps low-noise mode

Published in: 2018 IEEE International Solid – State Circuits Conference – (ISSCC)

High-resolution video has rapidly integrated into our daily life in the context of progress in camera, display, signal processing, and communication technologies. The uppermost video parameters standardized at this moment include 8K, 120-fps, 12b RGB, wide-color-gamut, and HDR. Although a camera that fulfills all these parameters has been reported based on 1.7-inch 33-Mpixel CMOS imagers [1], achieving a smaller form factor while also maintaining image quality is required from the standpoint of mobility, lens design, and depth of focus. In general, miniaturization of the imager causes degradation of the image quality metrics such as sensitivity, dynamic range, and resolution. We deliberated on these difficulties, and set a target optical format of 1.25 inch.



A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters

Published in: 2016 IEEE International Solid-State Circuits Conference (ISSCC)

There is an increasing demand for high-reality video systems. The ITU-R has standardized video parameters for ultra-high-definition TV (UHDTV), and the full-specification video signal stated in this international standard is prescribed as having a 7,680 (H) × 4,320 (V) pixel count, 120Hz frame frequency with progressive scanning, 12b tone reproduction, and wide color gamut. A 33Mpixel 120fps CMOS image sensor with a 12b column-parallel analog-to-digital converter (ADC) is reported in [1]. In addition to standard operation, higher sensitivity, smaller pixels, and a higher frame rate of 240fps or more are required for CMOS image sensors. Backside-illuminated stacked CMOS image sensors [2] are effective for simultaneously achieving both high sensitivity for small pixels and high operation speed. However, these stacked structures are still insufficient for high-frame-rate UHDTV image sensors since the pixel wafer and the ASIC wafer are connected by through-silicon vias in the peripheral area.



A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters (The 2013 Walter Kosonocky Award)

Published in: IEEE Transactions on Electron Devices ( Volume: 59 , Issue: 12 , Dec. 2012 )

A 33-megapixel 120-frames/s (fps) CMOS image sensor has been developed. The 7808 × 4336 pixel 2.8-μm pixel pitch CMOS image sensor with 12-bit, column-parallel, two-stage, cyclic analog-to-digital converters (ADCs) and 96 parallel low-voltage differential signaling output ports operates at a data rate of 51.2 Gb/s. The pipelined operation of the two cyclic ADCs reduces the conversion time. This ADC architecture also effectively lowers the power consumption by exploiting the amplifier function of the cyclic ADC. The CMOS image sensor implemented with 0.18-μm technology exhibits a sensitivity of 0.76 V/lx·s without a microlens and a random noise of 5.1 e rms – with no column amplifier gain and 3.0 e rms – with a gain of 7.5 at 120 fps while dissipating only 2.45 and 2.67 W, respectively.